• 837-Physical Design Engineer

Location Karnataka,Telangana Bengaluru,Hyderabad
Experience Range 3 - 7 Years
Qualification B. Tech, M. Tech, ME, BE Computer Science and Engineering (Computer Science)
Open

Job Description
About Us
Established in 1999, MosChip is the First Fabless Semiconductor company publicly traded in India with approx.20 years of experience. MosChip is a semiconductor and system design company with a focus on Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications. We have established ourselves as a preferred partner for technology and excellence. At MosChip, we strive to provide unparalleled service and support to our clients with on-time delivery being our strength and commitment. We aim to offer a unique combination of services and solutions giving them an advantage over competitors in their industry by aligning ourselves to the vision of our clients. Our client-driven approach focuses on all facets of the product development process, including not only the technology but also time-to-market and returns on investment (ROI). Supported by a focused team of engineering, technology, and domain experts, MosChip has embarked on a journey with a difference – to be a partner in growth.
Roles and Responsibility

 

Physical Design Engineer

 

COMPANY OVERVIEW:

 

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

 

REQUIRED SKILLS:

         He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.

         He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.

         Provide technical guidance, mentoring to physical design engineers.

         Interface with front-end ASIC teams to resolve issues.

         Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.

         Timing closure on DDR2/DDR3/PCIE interfaces.

         Excellent communication skills.

         Strong Background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.

         Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.

         Expertise in scripting languages such as PERL, TCL.

         Strong Physical Verification skill set.

         Static Timing Analysis in Primetime or Primetime-SI.

         Good written and oral communication skills. Ability to clearly document plans.

         Ability to interface with different teams and prioritize work based on project needs.

 

Education RequirementsB. Tech / M. Tech (ECE )

Experience3 to 7 Years

LocationHyderabad & Bangalore

ShiftGeneral

Work WeekMonday to Friday

 

Quick Links:

Who we are? https://www.youtube.com/watch?v=4nvbzE-eUGk

How we train? https://www.youtube.com/watch?v=Yy5GtKP7ozk

Contact: recruit@moschip.com

 

Recruiter Name MosChip
Recruiter Email Id Recruit@moschip.com
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