Physical Design Engineer
COMPANY OVERVIEW:
MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.
REQUIRED SKILLS:
• He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
• He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
• Provide technical guidance, mentoring to physical design engineers.
• Interface with front-end ASIC teams to resolve issues.
• Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
• Timing closure on DDR2/DDR3/PCIE interfaces.
• Excellent communication skills.
• Strong Background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.
Education Requirements•B. Tech / M. Tech (ECE )
Experience•3 to 7 Years
Location•Hyderabad & Bangalore
Shift•General
Work Week•Monday to Friday
Quick Links:
Who we are? https://www.youtube.com/watch?v=4nvbzE-eUGk
How we train? https://www.youtube.com/watch?v=Yy5GtKP7ozk
Contact: recruit@moschip.com
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