• Senior Engineer - Core Platform DDR

Location Karnataka,Tamil Nadu,Telangana Bengaluru,Chennai,Hyderabad
Experience Range 3 - 5.5 Years
Qualification B.Tech, M.Tech, B.E., M.E.

Skills Core BSP, DDR, JTAG, Trace, RTOS, DRAM
Job Description
About Us
Established in 1999, MosChip is the First Fabless Semiconductor company publicly traded in India with approx.20 years of experience. MosChip is a semiconductor and system design company with a focus on Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications. We have established ourselves as a preferred partner for technology and excellence. At MosChip, we strive to provide unparalleled service and support to our clients with on-time delivery being our strength and commitment. We aim to offer a unique combination of services and solutions giving them an advantage over competitors in their industry by aligning ourselves to the vision of our clients. Our client-driven approach focuses on all facets of the product development process, including not only the technology but also time-to-market and returns on investment (ROI). Supported by a focused team of engineering, technology, and domain experts, MosChip has embarked on a journey with a difference – to be a partner in growth.
Roles and Responsibility


Core Platform – DDR Engineer




MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.



         The charter of the Core BSP-DDR SW System team is to ensure that the end-product qualifies the defined acceptance criteria for DDR by meeting stability, Power and Performance Goals.

         Strong understating of system level test methodologies and run validations on mobile systems.

         The position involves Understanding of SOC Architecture and DDR SW Systems, identifying, and debugging DDR systems issues (memory corruptions, Memory Lockups, Bit flips, memory

         leaks etc..) reported by memory validation and running system level validations tests.

         The engineer would have opportunity to interact with different SW & HW teams to understand DDR systems.

         Good analytical / problem solving / sound reasoning skills

         Good understanding SOC systems knowledge level tests validation methodologies.

         Good understanding in working android environment. Experience of core BSP driver level development and debug

         Good understating of working debug tools like JTAG/TRACE. Awareness of RTOS operating system fundamentals / processor architecture /embedded system and microprocessor concepts.

         Understanding of DRAM technologies (LPDDR&PCDDR) and working on DRAM interface signal analysis is big plus

         The candidate is expected to be self-driven to quickly get up to speed on various aspects of DDR validation & flexible to take-up tasks as per the project needs


Education Requirements            B. Tech / M. Tech (ECE)

Experience                                                3 to 7 Years

Location                                                      Hyderabad & Bangalore

Shift                                                                General

Work Week                                                    Monday to Friday


Quick Links:


Who we are? https://www.youtube.com/watch?v=4nvbzE-eUGk

How we train? https://www.youtube.com/watch?v=Yy5GtKP7ozk



Contact: Recruit@moschip.com


Recruiter Email Id careers@moschip.com
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